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EM MICROELECTRONIC - MARIN SA
V6108
40 Segment Static LCD Driver
Description
This V6108 is a CMOS integrated circuit that drives LCD. The circuit drives up to 40 LCD segments from a serial clocked input. It has a serial output for cascading to further drives. The serially clocked data is parallel loaded into latches under control of the strobe pin. The latched data determines which segments are ON or OFF. Any segments output can be used to drive a backplane. A blank function is provided to clear the display.
Features
Serial data input / output Low dynamic current, 5 A max. Low standby current , 1 A max. Separate input and display voltages Wide power supply range : VDD (logic) 2 to 8V, VLCD (display) VDD to 12V On-chip latches separate control and display sections Drives up to 40 LCD segments in direct drive Crossfree cascadable Schmitt Trigger on the inputs 30 ns (typ.) glitch filter on every input High noise immunity Segment outputs short circuit protected LCD blanking function -40 to +85C temperature range On request extended temperature range, -40 to +125C QFP52 and TAB packages
Applications
Balance and scales Automotive displays Utility meters Large displays Pagers Portable, battery operated products Telephones
Typical Operating Configuration
Pin Assignment
Fig. 1
Fig. 2
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V6108
Absolute Maximum Ratings
Parameter Symbol Conditions Logic supply voltage VDD -0.3V to +10V LCD supply voltage (Note1) VLCD -0.3V to +14V Voltage at DI, CLK, STR, FR, VLOGIC -0.3V to VDD + 0.3V R, DO Voltage at S1 to S40 VDISP VDD to VLCD + 0.3V Storage temperature range TSTO -65 to 150C Power dissipation PMAX 100 mW Maximum electrostatic discharge to MIL-STD-883C VSmax 1000V method 3015.7 with ref. to VSS Max. soldering conditions TS 250C x 10s
Table 1
Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level.
Operating Conditions
Parameter Operating Temperature (Note 1) Logic supply voltage LCD supply voltage Symbol TA VDD VLCD Min -40 2.0 VDD Max +125 8 12 Unit C V V
Table 2
Note 1 : VLCD has to be higher or equal to VDD Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Note 1 : The maximum operating temperature is confirmed by sampling at initial device qualification . In production, all devices are tested at +85C. On request devices tested at +125C can be supplied
Electrical Characteristics
Unless otherwise specified: VDD= 5V 10%, VLCD= 12V and TA=-40 to +85C. Parameter Symbol Conditions Min Static supply current IDD See note 1 See note 1 Static supply current ILCD See note 1 & 2 Dynamic supply current IDD See note 1 & 3 Dynamic supply current ILCD All input Signals Low level input voltage VIL High level input voltage VIH 3.8 Leakage input current IIL VIN=VSS or VIN=VDD Data Output DO High level output voltage VOH VDD -100 IH=100A VDD=VLCD =4.5V Low level output voltage VOL IL=100A VDD=VLCD =4.5V Driver Output S1...S40 VSH High level output voltage VLCD -100 IH=20A VDD=VLCD =4.5V VSL Low level output voltage IL=20A VDD=VLCD =4.5V Short Circuit Current ISC only one output Note 1: Tested with VIL = VSS , VIH = VDD Note 2: Tested with fCL = 100kHz, FDI = 50kHz, 50 pF on each segment Note 3: Tested with fFL = 64Hz, fCL = 0Hz, 50 pF on each segment Typ 0.1 0.1 55 0.6 Max 1 1 75 5 0.8 3.5 1 Unit A A A A V V A mV mV mV mV mA
Table 3
VSS +100
0.9
VSS +100 2
Timing Characteristics
Unless otherwise specified: VDD= 5V 10%, VLCD= 12V and TA=-40 to +85C. Parameter Symbol Conditions Clock high pulse width tCH Clock low pulse width tCL tCR Clock and FR rise time tCF Clock and FR fall time Data input setup time tDS Data input hold time tDH Data output propagation tPD CLOAD = 50pF CLK falling to STR rising tP STR falling to CLK falling tD STR pulse width tSTR FR frequency fFR tSF Delay S1 - S40 fall time tSR Delay S1 - S40 rise time Note 1: Recommended frame frequency Note 2: Maximum test frequency
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Min 500 500
Typ
Max
500 500 250 0 600 50 250 200 64 Hz (note1) 0.5 2.9 1 (note2) 1 5 800
Unit ns ns ns ns ns ns ns ns ns ns mHz s s
Table 4
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V6108
Timing Waveforms
Fig. 3
VOL S1....S40 versus VLCD at -40, +25C and +85C.
Fig. 4
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V6108
VOH S1....S40 versus VLCD at -40, +25C and +85C.
Fig. 5
VOL DO versus VDD at -40, +25C and +85C.
Fig. 6
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V6108
VOH DO versus VDD at -40, +25C and +85C.
Fig. 7
Block Diagram
Pin Assignments
Name S1....S40 VLCD VDD FR DI DO CLK STR R VSS Function Segment drive outputs Power supply for the LCD Power supply for logic Input for segment frequency control Serial data input Serial data output Clock input Strobes the input data into the output latches Display blank control input Supply ground
Table 5
Fig. 8
Note 1: F = Noise Filter Note 2: LS = Voltage Level Shifter
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V6108
Functional Description
Supply voltages VLCD, VDD , VSS VDD is the positive supply line for the logic and VLCD for the display signals. VLCD has to be equal or higher than VDD . All voltages are specified relative VSS. Data Input / Output (DI / DO) The data input pin (DI) accepts serial data from the data source. The data is clocked in a rate determined by the clock input frequency (CLK). A logic "1" on DI corresponds to a visible segment when the backplane is driven by a signal corresponding to logic "0". The data at DO is equal to the data at DI delayed by 40 clock periods. In order to cascade devices the DO of one chip must be connected to DI of the following chip (see Fig.1). CLK Input The clock input pin (CLK) is used to clock the DI serial data into the 40-bit shift register. Loading, shifting and outputting of the data occurs at the falling edge of this clock (see Fig.3). When cascading devices , all CLK lines should be tied together. STR Input The strobe input pin (STR) is used to latch the input data shifted into the 40-bit shift register. The latched data is held for display. A logic "1" on the STR input transfers the data contained in the shift register cells to the corresponding latches. The latches remain open during the whole time STR remains at logic "1". When cascading devices the STR lines should all be connected. R Input When R is active (high), the display is blanked: all segment outputs are tied VSS.. R does not clear the information in the latches. Segment Driver The number of segment drivers available on the chip is 40. Each segment driver can be used as backplanedriver. If two or more drivers are connected together, care must be taken to ensure the drivers do not cause circuit malfunction by driving one against the other. FR Input This input controls the segment output switching frequency according to Table 6. It must be connected to an external clock signal. When cascading devices, their FR inputs may all be connected to a common signal. Segment Switching Table Signal Segment Voltage Latched Signal (DI) 0= Vss 1= VLCD 0= VIL 1= VIH FR 0 0 0 0 1 1 1 0 1 1 1 0
Table 6
Typical Applications
Type V6108 Circuits Driving a 79 Segment Display
Fig.9
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V6108
Cascaded V6108 TAB for Direct Drive Application
Fig.10
Package and Ordering Information
Dimensions of Chip Form
Dimensions in microns Fig.11 Chip size is X = 3302 by Y= 2159 microns or X = 130 by Y = 85 mils Note : The origin (0,0) is the lower left coordinate of center pads. The lower left corner of the chip shows distances to origin.
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V6108
Side view and recommended Solder Area
Fig.12
Package and Ordering Information The V6108 is available in the following packages: When ordering, please specify the complete part number and package.
QFP52, pin plastic package TAB, tape automated bonding Chip form
V6108 52F V6108 TAB V6108 Chip *
*on request
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
(c) EM Microelectronic-Marin SA, 09/04, Rev.C
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